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rev. 1.10 1 march 12, 2015 rev. 1.00 pb march 12, 2015 HT24LC128 cmos 128k 2-wire serial eeprom features ? operating voltage: 2.2v~5.5v for temperature -40?c to +85?c ? memory capacity: 128k (16k8) ? 2-wire i 2 c serial interface ? write cycle time: 5ms max. ? automatic erase-before-write operation ? partial page write allowed ? 64-byte page write modes ? write operation with built-in timer ? hardware controlled write protection ? 40-year data retention ? 10 6 erase/write cycles per word ? 8-pin dip/sop/tssop package description the HT24LC128 device is a 128k-bit 2-wire serial read/write non-volatile memory device manufactured using a cmos foating gate process. its 128k bits of memory are organized into 16k words and each word is 8 bits. the device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. up to eight HT24LC128 devices may be connected to the same two-wire bus. the HT24LC128 is guaranteed for 1m erase/write cycles and 40-year data retention. block diagram

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? ?? ? ? - ? pin assignment pin description pin name type description a0~a2 i address inputs sda i/o serial data scl i serial clock input wp i write protect vss pwr negative power supply, ground vcc pwr positive power supply
rev. 1.10 2 march 12, 2015 HT24LC128 absolute maximum ratings supply voltage ........................ v ss ?0.3v to v ss +6.0v input voltage ............................ v ss ?0.3v to v cc +0.3v storage temperature ........................... ?50c to 125c operating temperature ......................... ?40c to 85c note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c characteristics ta=-40oc to 85oc symbol parameter test condition min. typ. max. unit v cc conditions v cc operating voltage -40oc to 85oc 2.2 5.5 v i cc1 operating current 5v read at 400khz 2 ma i cc2 operating current 5v write at 400khz 5 ma v il input low voltage -0.45 0.3v cc v v ih input high voltage 0.7v cc v cc +0.5 v v ol output low voltage 2.2v i ol =2.1ma 0.4 v i li input leakage current 5v v in =0 or v cc 1 a i lo output leakage current 5v v out =0 or v cc 1 a i stb standby current 5v v in =0 or v cc 3 a sda, scl=vcc a0, a1, a2, wp=vss 1 a 2.2v v in =0 or v cc 2 a sda, scl=vcc a0, a1, a2, wp=vss 1 a c in input capacitance (see note) f sk =1mhz @ 25?c 6 pf c out output capacitance (see note) f sk =1mhz @ 25?c 8 pf note: these parameters are periodically sampled but not 100% tested.
rev. 1.10 3 march 12, 2015 HT24LC128 a.c characteristics ta=-40oc to 85oc symbol parameter remark v cc =2.2~5.5v v cc =2.5~5.5v unit min. max. min. max. f sk clock frequency 400 1000 khz t high clock high time 600 400 ns t low clock low time 1200 600 ns t r sda and scl rise time note 300 300 ns t f sda and scl fall time note 300 300 ns t hd:sta start condition hold time after this period the frst clock pulse is generated 600 250 ns t su:sta start condition setup time only relevant for repeated start condition 600 250 ns t hd:dat data input hold time 0 0 ns t su:dat data input setup time 150 100 ns t su:sto stop condition setup time 600 250 ns t aa output valid from clock 900 600 ns t buf bus free time time in which the bus must be free before a new transmission can start 1200 500 ns t sp input filter time (sda and scl pins) noise suppression time 50 50 ns t wr write cycle time 5 5 ms endurance 25oc, page mode 5.0v 1,000,000 write cycles note: these parameters are periodically sampled but not 100% tested. for relative timing, refer to timing diagrams.
rev. 1.10 4 march 12, 2015 HT24LC128 functional description pin function ? serial clock C scl the positive edge of the scl input is used to clock data into the eeprom device. the negative edge is used to clock data out of the device. ? serial data C sda the sda pin is bidirectional for serial data transfer. the pin is open drain driven and may be wired-or with any number of other open drain or open collector devices. ? address inputs C a0, a1, a2 the a2, a1 and a0 pins are device address inputs that are hard wired or left not connected. when the pins are hard wired, as many as eight 128k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). the code for the selected device is setup by connecting these inputs to either vss or vcc. if any pin is left unconnected in a floating state will be internally read as having a low input, vss, value. ? write protect C wp the HT24LC128 has a write protect pin that provides hardware data protection. the write protect pin allows normal read/write operations when connected to vss or left foating. when the write protect pin is connected to vcc, the write protection feature is enabled and operates as shown in the following table. wp pin status protect array v cc full array C 128k v ss or foating normal read/write operations memory structure the device is internally structured into 16k 8-bit words. a 14-bit data word address is required for word addressing. device operation ? clock and data transition data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. ? start condition a high-to-low transition of sda with scl high is a start condition which must precede any other command (refer to start and stop definition timing diagram). ? stop condition a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (refer to start and stop definition timing diagram). ? acknowledge all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has received each word. this happens during the ninth clock cycle. sda scl data allowed to change start condition stop condition no ack state address or acknowledge valid start and stop defnition timing diagram device addressing the 128k eeprom device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation. the device address word consists of a mandatory one, zero sequence for the frst four most signifcant bits (refer to the diagram showing the device address). this is common to all the eeprom devices. the 128k eeprom uses the three device address bits a2, a1, a0 to allow as many as eight devices on the same bus. these bits are compared to their corresponding hard wired input pins. the 8th bit device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. if the comparison of the device address is successful, the eeprom will output a zero ack bit. if not, the device will return to the standby state.
rev. 1.10 5 march 12, 2015 HT24LC128 write operations ? byte write a write operation requires two data word addresses following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. after receiving the 8-bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom will execute an internally-timed write cycle to the non-volatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write operation is completed (refer to byte write timing). ? page write the 128k eeprom is capable of a 64-byte page write. a page write is initiated in the same way as a byte write, but the microcontroller does not send a stop condition after the frst data word is clocked in. instead, after the eeprom acknowledges the receipt of the frst data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition (refer to page write timing). the data word address lower 6 bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data words are transmitted to the eeprom, the data word address will roll over and previous data will be overwritten. ? acknowledge polling to maximize bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command has been sent. if the device is still busy implementing its write cycle, then no ack will be returned. the master can send the next read/write command when the ack signal has fnally been received.
? ? ? acknowledge polling fllow ? write protect the HT24LC128 device has a write-protect function. programming will be inhibited when the wp pin is connected to vcc. in this mode, the HT24LC128 device can be used as a serial rom. read operations the HT24LC128 device supports three read operations, namely, current address read, random address read and sequential read. during read operation execution, the read/write select bit should be set to 1. ? current address read the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address remains valid between operations as long as the chip power is maintained. the address will roll over during a read from the last byte of the last memory page to the first byte of the first page. the address will roll over during a write from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but generates a following stop condition (refer to current read timing).
rev. 1.10 6 march 12, 2015 HT24LC128 ? random read a random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the eeprom. the microcontroller must then generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller should respond with a no ack signal (high) followed by a stop condition (refer to random read timing). ? sequential read sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledgment. as long as the eeprom receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read continues. the sequential read operation is terminated when the microcontroller does not respond with a zero but generates a following stop condition.

byte write timing

? ? ? ? ?? page write timing

current read timing

? ?? ? ? ?? random read timing

sequential read timing
rev. 1.10 7 march 12, 2015 HT24LC128 timing diagrams

note: the write cycle time twr is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
rev. 1.10 8 march 12, 2015 HT24LC128 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package information. additional supplementary information with regard to packaging is listed below. click on the relevant section to be transferred to the relevant website page. ? further package information (include outline dimensions, product tape and reel specifcations) ? packing meterials information ? carton information
rev. 1.10 9 march 12, 2015 HT24LC128 8-pin dip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.355 0.365 0.400 b 0.240 0.250 0.280 c 0.115 0.130 0.195 d 0.115 0.130 0.150 e 0.014 0.018 0.022 f 0.045 0.060 0.070 g 0.100 bsc h 0.300 0.310 0.325 i 0.430 symbol dimensions in mm min. nom. max. a 9.02 9.27 10.16 b 6.10 6.35 7.11 c 2.92 3.30 4.95 d 2.92 3.30 3.81 e 0.36 0.46 0.56 f 1.14 1.52 1.78 g 2.54 bsc h 7.26 7.87 8.26 i 10.92
rev. 1.10 10 march 12, 2015 HT24LC128 8-pin sop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.012 0.020 c 0.193 bsc d 0.069 e 0.050 bsc f 0.004 0.010 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a f 6.00 bsc b 3.90 bsc c 0.31 0.51 c 4.90 bsc d 1.75 e 1.27 bsc f 0.10 0.25 g 0.40 1.27 h 0.10 0.25 0 8
rev. 1.10 11 march 12, 2015 HT24LC128 8-pin tssop outline dimensions
symbol dimensions in inch min. nom. max. a 0.047 a1 0.002 0.006 a2 0.031 0.039 0.041 b 0.007 0.012 c 0.004 0.006 d 0.114 0.118 0.122 e 0.252 bsc e1 0.169 0.173 0.177 e 0.026 bsc l 0.018 0.024 0.030 l1 0.039 bsc y 0.004 0 8 symbol dimensions in mm min. nom. max. a 1.20 a1 0.05 0.15 a2 0.80 1 1.05 b 0.19 0.30 c 0.09 0.16 d 2.90 3.00 3.10 e 6.40 bsc e1 4.30 4.40 4.50 e 0.65 bsc l 0.45 0.60 0.75 l1 1.0 bsc y 0.10 0 8
rev. 1.10 12 march 12, 2015 HT24LC128 copyright ? 2015 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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